Phase reversal pulse modulator and pulse compression filter for a coherent radar

ABSTRACT

A coherent, 13 bit phase reversal pulse modulator and pulse compression filter for increasing the range resolution of a coherent radar. The transmitted pulse is subdivided into equal duration bits, and as the pulse is being formed each bit may or may not be shifted in phase determined by a digital code generator. The range resolution of which this pulse reversal modulated pulse is capable is achieved by processing the radar return signal in an approximation to a matched filter.

3|; United States atem [151 3,680,104

Westawa [4 1 Jul 25 1972 54 PHASE REVERSAL PULSE [56] References CitedMODULATOR AND PULSE UNITED STATES PATENTS COMPRESSION FILTER FOR A3,090,953 5/1963 Frank ..343/17.2 PC COHERENT RADAR 3,217,324 11/1965Adamsbaum et al... .343/172 PC x [72] Inventor: Thomas A. westaway ProvoUtah 3,223,999 12/1965 Grogtnsky ..343/l7.2 R X [73] Assignee: TheUnited States of America as Primary x i -M l lm F- H l r represented bythe secretary of the Navy AUOI'HBY-R. Sciascia and Thomas Watson, Jr.

[22] Filed: July 22, 1970 57 ABSTRACT [21] Appl- 57,262 A coherent, 13bit phase reversal pulse modulator and pulse compression filter forincreasing the range resolution of a [52] us CL 343/17 2 PC 343/5 DPcoherent radar. The transmitted pulse is subdivided into equal [51 1 m(301s 9/233 duration bits, and as the pulse is being formed each bit mayor [58] Fieid 17 2pc may not be shifted in phase determined by a digitalcode 3 5 generator. The range resolution of which this pulse reversalmodulated pulse is capable is achieved by processing the radar returnsignal in an approximation to a matched filter.

Claims, 1 1 Drawing Figures 20 22 24 26 2a 1m STABLE no FREOUENCY/ IMSIGNAL e g 115E512 Dial/DE R V ISfl 61'J'i IO BAICl/fiBGENFfL M l JT XFEI E R 1 60 Mc our 719 52 55 I RESET a lMcDlGlTAL GATE l 30 COMMANDCOUNTER COMMAND A+B SELECT PUL5E56 i 213 8 JUN 54 W are 512; sec PULSES5 I024}; sec 32 34- 0- l536 u. sec o 2048;; Set:

MANUAL AUTO 62 ElgzEvfiNAL cone SET 36 1 2 1s 72 IBOPHASE SWHCH SHIFT(1/2 64 I I 1 a. 68112 10 mass; m/ i 38 SHOT REGISTER L' C L'ESE DIODERF COMMAND SWITCH 1 \74 NORMALLY OPEN as 40 1 v SHIFT 12 13 SHIFTREGISTER Q PATTERN GENERATOR 2 1 1 4a 42 l i as i l I 2 .2 B Afbiiii'lii F swmzm-zs ME IN PULSED COMPRESSION cmcunmr g9 re-i, msmu.UNIT sum 1 or 5 K'FTIME T AMPLITUDE O TIME FIG. 2

AMPLITUDE +1 UNIT :TIME

FIG. 3

A! A2 A3 AlxBl A2xB2 OUTPUT FIG. 4

INVENTOR.

THOAS A. WESTAWAY 0. may}.

ATTORNEY PHEME JULZS I972 3 680 10 SHEET 2 OF 5 For O t T minus 19123.68.10

SHEET 3 0F 5 A AMPLITUDE KT (K+I)T (K+4)T (K+5)T A O (K+2)T (K+3)T VFIG. 6

AAMPLITUDE FIG. 7

A AMPLITUDE FIG. 8

A AMPLITUDE PHASE REVERSAL PULSE MODULATOR AND PULSE COMPRESSION FILTERFOR A COHERENT RADAR STATEMENT OF GOVERNMENT INTEREST The inventiondescribed herein may be manufactured and used by or for the governmentof the United States of America for governmental purposes without thepayment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION The present invention relates to a pulsemodulator and filter for a coherent radar and more particularly to aphase-reversal pulse modulator and pulse compression filter forproviding good range resolution for a peak power limited radar.

Two pulse radar requirements are long range and good range resolution.To achieve long range in a peak power limited radar, it is necessary totransmit a long pulse at the peak output power of the transmitter. Thisis necessary because the maximum range of a radar is dependent on theamount of energy transmitted. Thus in a peak power limited radar, theamount of energy transmitted can be increased only by increasing theduration of the signal transmitted. For good range resolution, or theability to distinguish between closely spaced targets, it is necessaryto transmit a signal whose autocorrelation function has a short durationresponse. The duration of this response decreases as the bandwidthincreases. The historical approach to achieve good range resolution wasto narrow the transmitted pulse duration which increased the bandwidthof the information transmitted. in a peak power limited radar, a moredesirable approach would be to retain the long pulse duration andtransmit the wide pulse width of the narrow duration pulse by suitablemodulating the transmitted signal. If the reflected signal is applied toa device that performs autocorrelation, target resolution correspondingto the wide transmitted bandwidth is realized. In performingautocorrelation on the reflected signal, we are also attempting tomaximize the signal-to-noise ratio at the output of the autocorrelationdevice. A device which maximizes the output peak signal-to-noise ratiois called a matched filter. Any radar system transmitting a longduration pulse which has been suitably modulated to provide a good rangeresolution can achieve no greater maximum range than a radar systemtransmitting a short duration pulse with the same resolution and amountofenergy as the longer duration pulse.

(liven the following equation for a gated sine 1 l u(t) I wave where Aequals the maximum value of sine wave; (1) equals the radian frequencyof the sine wave; t equals time; 4) equals the phase shift in radians;and T, equals the pulse duration we see that there are three parameterswhich can be varied for a given pulse duration. They are A, w and 4).Since we are interested in transmitting the most energy possible from apeak power limited radar, A must be a constant. That means we are leftwith frequency w and phase to vary during the pulse duration to achievea wide bandwidth signal.

The method disclosed in this invention for obtaining good rangeresolution is phase (4;) modulation, and in particular, phase reversalmodulation of the pulse carrier frequency. The disclosure also describesa pulse compression filter which effectively performs autocorrelation(or cross correlation if the reflected signal is distorted) on the phasereversal modulated (hereinafter called phase coded) pulse.

In the phase coding method of achieving a wideband signal, as shown inthe present invention, the transmitted pulse is subdivided into equalduration bits. Then as the pulse is being formed, the pulse carrierfrequency in each bit may be given either 0 or of phase shiftcorresponding to the binary digits 1 or 0 for that bit as determined bya digital code generator. The range resolution of which this phasereversal modulated pulse is capable is achieved by processing the radarreturn signal in an approximation to a matched filter. Thisapproximation consists of a tapped delay line where there are the samenumber of taps as bits in the modulated pulse. The spacing between tapsis the same as the bit duration. Each tap is in series with a circuitwhich multiplies the tap signals by either +1 or 1. The effect ofmultiplying a bit with 0 phase shift by 1 is to give it 180 phase shift.Multiplying a bit by 180 phase shift by -1 gives the bit 0 phase shift.Multiplication of a bit by +1 leaves it unchanged. Whether themultiplying circuit in each tap is +1 or 1 is determined by the phasecoding of the corresponding bit in the time inverted transmitted pulse.The output of the multiplying circuits are summed to form the output ofthe filter. When the returned pulse is completely contained in the delayline, then each bit in the pulse is being tapped off and multiplied by+1 or --1 so will all bits appear at the summing junction with 0 phaseshift and add constructively to form a compressed pulse with the samewidth as a bit in the phase coded pulse. This approximation to a matchedfilter is called a pulse compression filter. The improvement in thesignal-to-noise ratio at the output of the pulse compression filterapproaches the theoretical signal-to-noise improvement for the coherentintegration of N pulses. In this case N equals the number of bits in thecoded pulse.

The 13-bit phase coder and pulse compression filter described in theinvention has a bit duration of 0.1 microseconds. The measurement ofrange is a measurement of the amount of time between a transmitted pulseand its echo. This round trip delay time is given by the equation:

where T,, time delay R range C= speed light which 3 X (10) meters persecond or approximately 1,000 X 10) feet per second The incrementalamount of time, AT,, to make the round trip ZAR is thus:

C AR ATM 1f the amount of time required between the leading edges of twoecho pulses is 0.1 microseconds, in order to resolve them as two echos,then Thus for a phase coded system with a 0.1 microsecond bit duration,the range resolution, A R, is approximately 50 ft.

SUMMARY OF THE INVENTION The present invention offers many improvementsover the shortcomings and weaknesses of similar prior art devices inthat it discloses a phase reversal pulse modulator and pulse compressionfilter which materially increases the range resolution of a coherentradar. By subdividing the transmitted pulse into 13 equal duration bits,shifting the bits according to a digital code generator, and then byprocessing the return pulse according to the same code the operation ofa pulse compression matched filter is effectively obtained.

OBJECTS OF THE INVENTION An object of the present invention is theprovision of a phase reversal pulse modulator and pulse compressionfilter for radars.

Another object of the invention is the provision of a pulse modulatorfor improving the range resolution of pulse radars.

Still another object of the present invention is the provision of thepulse modulator for achieving long range in a peak power limited radar.

Yet another object of the present invention is to provide a pulsemodulator in which the transmitted pulse is subdivided to equal durationbits.

Still another object of the present invention is the provision of apulse modulator in which the pulse carrier frequency in phase shiftedcorresponding to binary digits 1 or 0.

Still another object of the present invention is the provision of apulse modulator in which the phase is shifted according to a digitalcode generator.

Other objects and many of the attendant advantages of this inventionwill be readily appreciated as the same becomes better understood byreference to the following detailed description when considered inconnection with the accompanying drawings in which like referencenumerials designate like parts throughout the figures thereof andwherein.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a graphical presentationof a function as Hor +1 bit.

FIG. 2 shows a graphical presentation of a function as a or 1 bit.

FIG. 3 shows a graphical presentation of a three bit coded pulseof+1-(or+l+1l).

FIG. 4 shows the summing network used for the above three bit codedpulse.

FIG. 5 shows a graphical presentation of the sequence of events as thecoded pulse passes through the pulse filter.

FIG. 6 is a graphical presentation of the output of the summing network.

FIG. 7 shows a presentation ofa positive bit.

FIG. 8 shows a presentation ofa negative bit.

FIG. 9 shows the output of the pulse compression filter as a functionoftime.

FIG. 10 shows a block diagram of the pulse coding circuitry.

FIG. 11 shows a block diagram of the pulse compression filter.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawingswherein like reference characters designate like or corresponding partsthroughout the several views there is shown in FIG. 1 a graphicalpresentation of a +1 bit, and it will be noted that the function extendsabove the line for one unit and extends from K T to (K,+l )T along thetime line. Then in FIG. 2 which shows a bit the same unit extends belowthe time line this time extending from K T to (K +l)T. Now in FIG. 3there is shown a three bit coded pulse of +l+l and l are this time thereare two units above the line and one unit below the time line.

In FIG. 4 there is shown a summing network for the three bit coded pulseas would appear in FIG. 3. The transition horizontally from one columnto the next column (A1 to A2, A2 to A3) in the diagram represents thetime delay line with Al, A2, and A3 representing the tap out-puts. B1,B2 and B3 represent the multiplying factors for each tap and can beeither +1 or I. After multiplication in each tap, the multiplier outputsare summed to form the output of the pulse compression filter. Thevalues Bl, B2,and B3 are determined by time inverting the coded pulse.The time inverted pulse of this case then would be -l-l-. Thus B1=l andB2=B3=+l.

In FIG. 5 there is shown a series of diagrams indicating the sequence ofevents as the coded pulse passes through the pulse compression filter.

In FIG. 6 there is shown graphically how the outputs as presented inFIG. 5 would appear, and it can be seen that the first output ofl is oneunit below the line, then the second one is 0, followed by a third whichhas a +3 amplitude, fol lowed by a fourth which is 0, and then closingwith a fifth output of I In FIG. 7 there is shown graphically what theoutput of a bit from the transmitter would be like, and it is seen thatthe graph starts from 0, increases in a positive direction to a +1amplitude, then reverses to a l amplitude and continues along the timeline for a 0.1 microsecond time span. The reverse is shown in FIG. 8 andin this case the initial line starts from 0 and goes in a direction toI, then reverses to a +1 amplitude, and also continues for a 0.1microsecond time span. The difference between the and the bits beingthat the bit is out of phase with the bit.

Thus with the only difference between the and bits being the sign, it isseen that multiplying either of them by 1 will change the sign or thephase by 180. Multiplying either by +1 will leave the bit unchanged.Thus the preceeding explanation of the three bit pulse compression stillholds and the output ofthe pulse compression filter as a function oftime will be represented in FIG. 9.

Referring to FIG. I0 there is now shown a block diagram for the pulsecoding circuitry such as would be used to have the transmitted pulsesubdivided into equal duration bits. A l megacycle stable crystaloscillator 20 is connected to a l megacycle signal divider 22, oneoutput of which goes to a 10 power frequency multiplier 24, this in turnfeeding a 10 megacycle signal divider 26. One output from the divider 26is applied to a 6 power frequency multiplier 28 which delivers an outputof 60 megacycles, this output being applied to a hybrid junction 30. Oneoutput of hybrid junction 30 is produced at 32, this output beingimpressed upon a 180 phase shifter 36, and after the signal is shiftedby 36 it is applied to a diode RF switch 38 which in its deenergizedstate is normally open. A second output 34 from hybrid junction 30 isapplied as an input to a second diode RF switch 40, this switch likewisein its deenergized state being normally open. When diode switch 38 isclosed it produces an output on lead 44 which is applied as one input toa second hybrid junction 46, the second input to this junction beingproduced on a lead 42 when diode switch 40 is closed. The output ofsecond hybrid junction 46, which in effect is the summation of theoutputs on leads 44 and 42, is produced at a coded pulse output terminal48.

Within the broken line shown in FIG. 10 there is depicted a digital codegenerator 50 which not only determines the or sign of the subdividedequal duration bits from the transmitted pulse, but it also activatesthe RF switches in the pulse compression circuitry so that thiscircuitry will accurately pass the returning waveform bits as they arereflected from a distant target. An output from I megacycle signaldivider 22 is applied to a digital counter 52, the output of thiscounter being applied to a stepping switch 54 which is used to selectthe pulse repetition period of the transmitter as provided by repetitionpulse selector 56, the output of this selector being applied to a gatecommand 58 and then to a gate shift 60. A second input to gate shift 60is provided from 10 megacycle signal divider 26.

In order to provide a desired pulse code for the transmitter there isprovided an external code setter 62 which has a plurality of single poledouble throw switches, and in this illustration numbered between 1 and13 for the 13 bits of the pulser, the switches acting to work betweenground and -1 2 volts.

Also included with external code setter 62 is a momentary close switch64 which is used to start the sequence of events setting up the encoderas will be described more fully hereinafter. All of the outputs fromexternal code setter 62 are applied to a 13 shift register patterngenerator unit 66, which after processing the inputs from the codesetter provides two sets of outputs according to the predetermined code.One set of these outputs from pattern generator 66 are applied to RFswitches in the pulse compression circuitry as at 68, while a duplicateset of outputs are applied to a parallel-to-serial shift register 70. Atthe properly appointed time, gate 60 applies a signal to the shiftregister 70 and outputs from this register 70 are applied to a switchclose command 72 and also to another switch close command 74. Switchclose command 72 functions to operate diode RF switch 38 while switchclose command 74 functions to close diode RF switch 40.

The pulse coding circuitry can operate in either a manual or anautomatic mode, the type being determined by a single pole double throwswitch 76. When in the automatic mode of operation one side of switch 76is connected to the reset command 78 and also as another input tocommand gate48, and will likewise be connected to a shift command 80whose output forms another input to the pattern generators 66.

Turning now to FIG. 11 there is shown a block diagram of the pulsecompression filter. This pulse compression filter consists of a delayline 82 which is shown within the dotted lines, this delay line beingtapped at 13 points spaced at 0.1 microsecond intervals along the line.The radar return signals in the form of coded pulses are applied to thecompression filter at an input terminal 84. Tapping of the delay line isaccomplished by inserting an amplifier as at 86 at the proper places inthe delay line. These amplifiers (called tap amplifiers) have twooutputs, one output of which drives the next section of the delay linewhile the second output supplies signals to a single pole double throwRF switch as at 88. It should be noted at this point that for the sakeof simplicity there are only two channels of the 13 tap points shown inFIG. 11. Digital code information as provided at output 68 from patterngenerators 66 are also applied to each of the RF switch and drivers 88and it may be pointed out again here that the outputs from patterngenerator 66 are applied to the delay line in the reverse order in whichthey were applied to the transmitter. In other words No. 13 is appliedto the beginning of the tap line and No. l to its end. Two outputs fromRF switch and driver 88 are applied to a hybrid junction 90 in eachchannel, the output of these junctions each being applied to a bufferamplifier 92 before they are all applied to a summing device 94 and acomposite compress pulse output is furnished at point 96.

Turning now to the operation of the pulse coding circuitry as shown inFIG. 10, all frequencies needed for timing in digital unit 50 and the 60megacycle signal from multiplier 28 to be phase coded, are derived froma stable 1 megacycle crystal oscillator 20 which has a stability in theorder of plus or minus five parts in to the 10th per day. The stableoutput from oscillator 20 is in turn applied to signal divider 22 thento multiplier 24 then to signal divider 26 and finally to frequencymultiplier 28 which has an output of the desired 60 megacycles. Themethod of forming the 13 bit, phase coded, pulse uses two diode RFswitches. The 60 megacycle signal from multiplier 28 is split equally ina hybrid junction 30 and applied to the input of two RF switches 38 and40. The signal to one of the RF switches, that is switch 38, must passthrough 180 phase shift cable 36 and therefore must travel through onehalf wave length more of cable than the signal to the other switch(diode RF switch 40). Thus the output of switches 38 and 40 will be 180out of phase. The closing of RF switches 38 and 40, and thus the phasecoding, is controlled by digital unit 50 through the operation of switchclose commands 72 and 74 respectively. The outputs of switches 38 and 40are applied to hybrid junction 46 where they are then summed in thishybrid junction to form a 13 bit phase coded pulse. Each bit is 0.1microsecond in duration and thus the 13 bit pulse will be 1.3microseconds in duration as produced at output point 48.

The digital pulse unit 50 is constructed in such a way that a 13 bitcoded pulse can be formed by entering the desired code on the frontpanel switches forming a part of external code setter 62, and by usingthe one-shot switch 64 to store the code in the unit. By placing theauto-manual switch 76 in the auto-position, the pulse coding will changeautomatically from pulse to pulse. For each bit in the 13 bit codedpulse, there is a seven bit binary shift register pattern generatorwhose cycle length is 127, these 13 shift register pattern generatorsforming the circuitry for component 66. These shift registers ofcomponent 66 shift once each pulse repetition period when in the automode so that they have completed a cycle in I27 pulse repetitionperiods. The outputs of the 13 shift register pattern generators fromcomponent 66 are applied to parallel to-shift register 70 and byappropriately taking assertion or negation outputs and storing them inthis parallel-to-serial shift register 70, a 13 bit Barker CODE(+HHlll+) is formed at the beginning of each pattern cycle. The gatedassertion and negation outputs of the final flip flop in the parallel toserial shift register 70 are the control signals for the RF diodeswitches 38 and 40 which form the phase coded pulse, through theoperation of switch close commands 72 and 74. When the gate pulse is notpresent on gate 60, both control lines (to switch commands 72 and 74)are at 0 volts and the RF switches 38 and 40 are open. When the gatepulse is present, the control lines switch between 0 volts and l 2 voltsas the code stored in the register is shifted out at a 10 Mc rate. Whenthe control line to RF switch 38 or 40 goes to -l 2 volts, the switch isclosed and RF is allowed to pass. In the auto mode of operation, the RFswitches 88 in the pulse compression filter (FIG. 11) receive the newcode information and switch the tapped signals to the proper inputs ofthe hybrid junctions l microsecond before the new phase coded pulsebegins forming, Thus the pulse compression filter is ready for the newlycoded pulse as soon as it is formed.

The pulse compression filter is shown in the block diagram in FIG. 11and it can be seen that the filter consists of a delay line 82 tapped at13 points spaced at 0.1 microsecond intervals along the line. Tapping isaccomplished by inserting an amplifier, such as 86, with two outputs,into the delay line at the proper place. One output of the amplifier 86(called a tap amplifier) drives the next section of the delay line andthe other output supplies the signal to a single pole double throw RFswitch 88. This RF switch 88 directs the signal to one of two inputs toa hybrid junction 90, There are four possible inputs (or outputs) in ahybrid junction. They could be labeled A, B, A+B, and A-B. By applyingthe tap signal to either the input A or B and taking the output at A-Bit is possible to multiply it by +1 or I. For example, if the signal isapplied to B, the output is then 0-B or 1 times the signal at input B.Similarly, by applying the signal to input A and no signal to B, theoutput will AO or +1 times the signal at A. The digital code unit 50 inFIG. 10 determines whether the tap signal is to be applied to input A orB of the hybrid junction in each tap. The A-B output of the hybridjunction is connected to a buffer amplifier 92 and the buffer amplifieroutputs are summed in a summing circuit 94 and amplified to form theoutput of the pulse compression filter as at 96.

From the above description of the structure and operation of the presentinvention it is obvious that there is disclosed therein a phase reversalpulse modulator and pulse compression filter for radars which providesconsiderable improvement over prior art radars in that it provides goodrange resolution and a maximum range for a peak power limited radar.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood, that within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described.

What is claimed:

1. A phase reversal modulator and pulse compression filter for a radarcomprising:

a stable source of pulses;

frequency multiplier means connected to the source of pulses to providepulses at a desired frequency higher than the stable source;

a first hybrid junction for receiving the output of the multiplier anddividing it into two equal outputs;

a first RF switch connected to one of the hybrid junction outputs;

a phase shifter connected to the other hybrid junction output;

a second RF switch connected to the phase shifter so that the inputs ofthe first and second RF switches are 180 out of phase;

a digital unit for operating the two RF switches;

a second hybrid junction for combining the outputs from the two RFswitches to produce a coded pulse output for the radar; and

a pulse compression filter also operated by the digital unit forcompressing the radar return pulses.

2. The device of claim 1 wherein the stable source of pulses is acrystal controlled oscillator.

3. The device of claim 2 wherein the digital unit comprises:

means for generating a binary pattern in response to a coded input; and,

means connected to said generating means for setting a code into saidgenerating means.

4. The device of claim 3 wherein:

the generating means comprises a binary shift register pattern generatorhaving a plurality ofinputs; and,

the code setting means comprises a plurality of two position switches,each switch being connected to one of the shift register patterngenerator inputs, the positions of the switches determining the code.

5. The device of claim 4 wherein the digital unit includes a parallel toserial shift register connected to the binary shift register patterngenerator to produce an output equal sequentially to the output of thegenerator.

6. The device of claim 5 wherein the digital unit includes a first meansto connect the serial shift register to the first RF switch and a secondmeans to connect the serial shift register to the second RF switch,according to the binary output of the serial shift register.

7. The device of claim 6 wherein the pulse compression filter includes:

a delay line having a plurality ofsections;

a-plurality of tap amplifiers spaced along the delay line,

each individual tap amplifier being disposed between two adjacentsections of the delay line, there being the same number of amplifiers asthere are bits in the transmitted pulse; and,

means to apply a return echo pulse to the front of the delay line.

8. The device of claim 7 wherein the pulse compression filter includes:

an RF switch connected to each tap amplifier;

a hybrid junction connected to each RF switch; and

a buffer amplifier connected to each hybridjurlction.

9. The device of claim 8 wherein the pulse compression filter includesmeans to connect each of the RF switches in the filter to a shaftregister pattern generator in the binary unit.

10. The device of claim 9 wherein the pulse compression filter includes:

a summing circuit connected to all of the buffer amplifiers;

and

output means connected to the summing circuit pulse output.

1. A phase reversal modulator and pulse compression filter for a radarcomprising: a stable source of pulses; frequency multiplier meansconnected to the source of pulses to provide pulses at a desiredfrequency higher than the stable source; a first hybrid junction forreceiving the output of the multiplier and dividing it into two equaloutputs; a first RF switch connected to one of the hybrid junctionoutputs; a 180* phase shifter connected to the other hybrid junctionoutput; a second RF switch connected to the phase shifter so that theinputs of the first and second RF switches are 180* out of phase; adigital unit for operating the two RF switches; a second hybrid junctionfor combining the outputs from the two RF switches to produce a codedpulse output for the radar; and a pulse compression filter also operatedby the digital unit for compressing the radar return pulses.
 2. Thedevice of claim 1 wherein the stable source of pulses is a crystalcontrolled oscillator.
 3. The device of claim 2 wherein the digital unitcomprises: means for generating a binary pattern in response to a codedinput; and, means connected to said generating means for setting a codeinto said generating means.
 4. The device of claim 3 wherein: thegenerating means comprises a binary shift register pattern generatorhaving a plurality of inputs; and, the code setting means comprises aplurality of two position switches, each switch being connected to oneof the shift register pattern generator inputs, the positions of theswitches determining the code.
 5. The device of claim 4 wherein thedigital unit includes a parallel to serial shift register connected tothe binary shift register pattern generator to produce an output equalsequentially to the output of the generator.
 6. The device of claim 5wherein the digital unit includes a first means to connect the serialshift register to the first RF switch and a second means to connect theserial shift register to the second RF switch, according to the binaryoutput of the serial shift register.
 7. The device of claim 6 whereinthe pulse compression filter includes: a delay line having a pluralityof sections; a plurality of tap amplifiers spaced along the delay line,each individual tap amplifier being disposed between two adjacentsections of the delay line, there being the same number of amplifiers asthere are bits in the transmitted pulse; and, means to apply a returnecho pulse to the front of the delay line.
 8. The device of claim 7wherein the pulse compression filter includes: an RF switch connected toeach tap amplifier; a hybrid junction connected to each RF switch; and abuffer amplifier connected to each hYbrid junction.
 9. The device ofclaim 8 wherein the pulse compression filter includes means to connecteach of the RF switches in the filter to a shaft register patterngenerator in the binary unit.
 10. The device of claim 9 wherein thepulse compression filter includes: a summing circuit connected to all ofthe buffer amplifiers; and output means connected to the summing circuitpulse output.